Stop seizures
before they spread.

Technical Specifications

Pipeline OverviewNeural recordings from each electrode, implanted directly into brain tissue, are sampled using 16-bit ADCs and transferred from the host computer to the FPGA in Intan-defined, fixed-size, channel-interleaved data blocks. The designed pipeline collects this data using a proprietary RHD format and streams it to the seizure-detection hardware (RTL) implementation under test. The runtime outputs are collected on the host in a timestamp-bounded event format that marks seizure start and end boundaries for further in-vivo verification. Upon detection, charge-balanced biphasic stimulation pulses are delivered back through the implanted electrodes, disrupting cortical synchrony and interrupting the seizure before it generalizes.

Seizure ProcessingThe RTL implementation decomposes seizure detection into a deeply pipelined, multi-stage datapath optimized for hardware concurrency and per-channel independence. Seizure detection consists of three independent modules (NEO, THR, and GATE) that perform fixed-point arithmetic and threshold evaluation at a single-sample-per-clock throughput per channel. First, each channel maintains a dedicated sliding-window, three-sample history buffer used to compute the nonlinear energy operator (NEO), a signal transformation that highlights transient oscillatory activity associated with seizure onset. Downstream of the configurable threshold (THR), which marks high-oscillation detections, a gating state machine tracks detection persistence over time using configurable transition counters and inactivity windows. This logic converts transient, sample-level detections into temporally bounded seizure events while preserving channel-level isolation. The modular separation between peripheral communication logic and datapath computation allows independent timing closure and facilitates future migration toward an ASIC-based physical design pipeline without a PC in the loop.

Software StackWe implement a host-side software stack that complements the hardware processing by providing configuration management and post-processing visualization. A graphical user interface enables runtime parameter tuning, batch file processing, and visualization of detection intervals across channels and recording sessions. Hardware-generated event packets are decoded and organized into structured output files that allow cross-referencing between detected seizure regions and raw waveform recordings.

Technical Specifications

Pipeline OverviewNeural recordings from each electrode, implanted directly into brain tissue, are sampled using 16-bit ADCs and transferred from the host computer to the FPGA in Intan-defined, fixed-size, channel-interleaved data blocks. The designed pipeline collects this data using a proprietary RHD format and streams it to the seizure-detection hardware (RTL) implementation under test. The runtime outputs are collected on the host in a timestamp-bounded event format that marks seizure start and end boundaries for further in-vivo verification. Upon detection, charge-balanced biphasic stimulation pulses are delivered back through the implanted electrodes, disrupting cortical synchrony and interrupting the seizure before it generalizes.

Seizure ProcessingThe RTL implementation decomposes seizure detection into a deeply pipelined, multi-stage datapath optimized for hardware concurrency and per-channel independence. Seizure detection consists of three independent modules (NEO, THR, and GATE) that perform fixed-point arithmetic and threshold evaluation at a single-sample-per-clock throughput per channel. First, each channel maintains a dedicated sliding-window, three-sample history buffer used to compute the nonlinear energy operator (NEO), a signal transformation that highlights transient oscillatory activity associated with seizure onset. Downstream of the configurable threshold (THR), which marks high-oscillation detections, a gating state machine tracks detection persistence over time using configurable transition counters and inactivity windows. This logic converts transient, sample-level detections into temporally bounded seizure events while preserving channel-level isolation. The modular separation between peripheral communication logic and datapath computation allows independent timing closure and facilitates future migration toward an ASIC-based physical design pipeline without a PC in the loop.

Software StackWe implement a host-side software stack that complements the hardware processing by providing configuration management and post-processing visualization. A graphical user interface enables runtime parameter tuning, batch file processing, and visualization of detection intervals across channels and recording sessions. Hardware-generated event packets are decoded and organized into structured output files that allow cross-referencing between detected seizure regions and raw waveform recordings.